In order to reduce the cost of semiconductor products, particularly memories, it is necessary to increase the degree of integration and miniaturization of the integrated circuits. A comparative study of the scaling between dynamic random access memories, DRAMs, and static random access memories, SRAMs, shows that the degree of integration achieved in SRAMs is less than that achieved in DRAMs.
The degree of integration of DRAMs has been enhanced with the use of improved three-dimensional semiconductor structures. Three dimensional semiconductor structures can be used for isolation purposes, for the integration of capacitors, or for the integration of transistors which are formed either within or above the silicon substrate. Three-dimensional structures formed within a silicon substrate are typically associated with a silicon trench, and structures formed above the silicon substrate are typically formed in overlying layers of polysilicon which may be recrystallized to form single crystal silicon. The overlying layers of silicon, formed in the manner described, are referred to as "silicon-on-insulator" or SOI.
Improvements in the degree of integration of DRAMs have largely been due to a reduction of circuit area required to form memory cell storage capacitors. The memory cell area is typically reduced by either forming capacitors in silicon trenches which are etched into a silicon substrate, or by stacking capacitors overlying a layer of silicon.
SRAM memory cells, in contrast to DRAM memory cells, do not utilize storage capacitors and, therefore, have not benefited from the improvements in DRAM integration. In contrast with a DRAM memory cell circuit which has a single transistor and a storage capacitor, the SRAM memory cell circuit has an electronic latch circuit constructed from two inverter circuits. The area of an SRAM memory cell can be minimized by using a simple latch design. An example of a simple latch design that encompasses a small circuit area is a latch having two transistors and two load resistors. A disadvantage of this circuit is that a high standby current results when the latch has power applied to it. A further complication results if the load resistances are increased to minimize the standby current. Under these circumstances, the latch becomes inherently unstable and the output is unpredictable.
A full CMOS latch contains two N-channel transistors and two P-channel load transistors. The latch can be considered as two inverters with each inverter having one N-channel transistor and one P-channel load transistor. The load current flowing in each inverter is negligible because the inverter has two transistors of opposite conductivity type. Unfortunately, a full CMOS latch design requires a larger area of silicon substrate for the integration of four transistors. In order to achieve the benefits of a full CMOS design, while at the same time achieving a high degree of integration, it is necessary to reduce the area of silicon substrate required to integrate the latch. A process known as "silicon-on-insulator" or SOI process can be used to remove two of the P-channel transistors from the silicon substrate and to form them in a layer of silicon overlying a conventional transistor structure formed in the silicon substrate.
The removal of two P-channel transistors from the silicon substrate reduces the area of silicon substrate required for the integration of the latch. However, the improvements gained are still inadequate as compared with the advances in the degree of integration obtainable in DRAM technology.